How to Route Differential Pairs on a PCB

A differential pair that looks neat on screen can still fail at the interface. At multi-gigabit data rates, a small change in spacing, an unnecessary via or a split in the reference plane can introduce reflections, mode conversion and timing error. Knowing how to route differential pairs means treating the two traces, their dielectric environment and their return path as one controlled transmission structure.

The required precision depends on the signalling standard, edge rate, link length and allowable loss. A short low-speed differential connection can tolerate more variation than a USB 3, Ethernet, PCIe, MIPI or high-speed sensor interface. The design objective is the same: preserve the intended differential impedance, keep the conductors electrically balanced and avoid discontinuities that convert useful differential energy into unwanted common-mode noise.

Start with the stack-up, not the traces

Differential routing begins before component placement. Trace width, pair spacing, copper thickness, solder mask and the distance to the nearest reference plane all affect impedance. These dimensions must come from the PCB fabricator's approved stack-up and impedance model, not from a generic calculator or a rule copied from another board.

A pair on an outer layer is usually routed as edge-coupled microstrip, while an inner-layer pair is commonly stripline. Microstrip is accessible and convenient for short runs, but is more exposed to its surroundings and may radiate more readily. Stripline is better shielded by adjacent planes and often offers more predictable field containment, although layer transitions and vias need careful planning.

Agree the target impedance with the interface specification and fabricator. Many systems use 100-ohm differential impedance, but this is not universal. The relevant value is the nominal differential impedance at the receiver and transmitter, including the tolerance the channel can accept. Specify controlled impedance on the fabrication drawing where the application requires it, then ensure the layout rules reflect the fabricator's actual geometry.

Keep the geometry continuous

Once width and spacing are defined, hold them wherever practical. Do not neck one conductor down to pass a pad while leaving the other unchanged. Do not widen both traces casually to fill available space. Either change alters impedance, and asymmetrical changes also upset the electrical balance of the pair.

Copper pours, adjacent signals, component pads and board edges can all disturb the fields around a differential pair. Keep other routing at a sensible clearance from the pair, particularly alongside long parallel sections. The required clearance depends on the layer construction and signal speed, but a practical rule is to keep unrelated conductors far enough away that their coupling is insignificant compared with the coupling within the pair.

How to route differential pairs through the board

Route both conductors together from source to destination. Modern PCB tools support differential-pair classes that enforce width, gap, length and clearance rules. Use those rules rather than manually routing one trace and attempting to replicate it beside the other. This reduces layout variation and makes design review considerably faster.

Maintain a continuous reference plane under the entire route. Differential signals do not eliminate return current. In an ideal pair, much of the high-frequency return current couples between the two conductors, but imbalance and common-mode energy still require a low-inductance reference path. A plane split, void, slot or narrow neck below the pair can cause a sharp impedance disturbance and increased radiation.

Where the pair must change layers, move both traces together and use matched vias. Keep the via geometry, antipads and pad sizes symmetrical. If a reference plane changes at the transition, place suitable stitching vias close to the signal vias so return current can transfer between reference planes with minimal loop area. The exact arrangement depends on whether the adjoining planes are ground or power planes and on the stack-up, so it should be reviewed as part of the complete return-path design.

Use bends and corners consistently

Differential pairs do not need decorative arcs, but they do need symmetry. Use 45-degree bends or smooth curves where the routing direction changes. Avoid sharp 90-degree corners, particularly in controlled-impedance high-speed routes, because they create a local geometry change and can make one conductor electrically longer than the other.

When a pair turns, retain the intended separation through the bend. A tight inside corner can reduce the gap and increase coupling, while a stretched outside trace creates skew. PCB design software can usually maintain pair spacing through corners, but the result should still be inspected around dense connector footprints and fine-pitch devices.

Avoid unnecessary via transitions. Each via adds inductance, capacitance and a short impedance discontinuity. At sufficiently high frequencies, via stubs can resonate and degrade the channel. Back-drilling, blind vias or carefully chosen layer assignments may be justified for demanding links, but they add cost and manufacturing constraints. Use them where signal-integrity analysis supports the decision, rather than as a default feature.

Match electrical length, not just measured length

Length matching is often misunderstood. The need is to control timing skew between the positive and negative conductors, not to make every visual path identical. Two traces of equal physical length can have different propagation delay if they travel through different dielectric conditions, pass close to different copper features or use unequal via structures.

Follow the interface specification for allowable intra-pair skew. For many practical routes, keeping the two conductors closely coupled and geometrically identical will naturally maintain acceptable skew. Where tuning is required, add it in a controlled region with adequate clearance from other high-speed nets. Avoid scattering small tuning patterns along the route, especially near connectors, vias or breakouts where the pair is already disturbed.

Serpentine tuning has a trade-off. Closely packed meanders can couple to themselves, changing delay and impedance while adding loss. Use broad, well-spaced tuning sections where possible, and apply the same approach to each conductor when the routing topology demands it. In some cases, changing component placement or selecting a better layer path is preferable to adding extensive length compensation.

Treat pads, connectors and flex transitions as part of the channel

The transmission line does not stop at the end of the routed trace. Connector launches, BGA escapes, AC-coupling capacitor pads, ESD devices, test points and flex interconnects all contribute to the channel response. A well-routed pair can lose performance at a poorly designed transition.

Keep series components aligned and symmetrical. If capacitors or protection devices are required on both conductors, place them with equivalent pad geometry and short, matched connections. Avoid long stubs to test pads. For high-speed interfaces, use purpose-designed probing points or omit test access where the signal-integrity requirement makes conventional pads unsuitable.

Flex and rigid-flex assemblies deserve the same impedance discipline as rigid boards. The bend area, coverlay, stiffeners, connector geometry and transition from rigid PCB to flex all influence practical performance. This is particularly relevant in compact AI vision, robotics and sensor products, where a moving interconnect may carry both high-speed data and tight mechanical constraints. A custom flex design should be developed alongside the PCB layout, not added after routing is complete.

Cocom supports this engineering approach with custom PCB and flex interconnect development for systems where mechanical packaging and controlled signal performance must work together.

Verify before releasing manufacturing data

A differential-pair rule check is necessary, but it is not sufficient. Review the physical route at maximum zoom and inspect every change in layer, reference plane, width, spacing and nearby copper environment. Confirm that polarity is correct from transmitter to receiver, especially through connectors and flex assemblies where a mirrored pinout can create expensive rework.

For critical channels, use field-solver-based impedance extraction and signal-integrity simulation. These tools help assess insertion loss, return loss, crosstalk, via effects and eye performance using the actual stack-up and component models. They also reveal when a theoretical layout rule is no longer adequate for the selected data rate or channel length.

Before fabrication, provide the fabricator with the controlled-impedance requirements, layer stack-up expectations and any test requirements. Confirm achievable impedance tolerance, copper weights, material options and whether the chosen geometry remains manufacturable across the intended production volume. A layout that meets nominal impedance but cannot be built consistently is not a production-ready design.

The strongest differential routes are rarely the most elaborate. They are planned early, governed by a real stack-up, kept symmetrical through every transition and checked as complete channels. That discipline gives high-speed hardware the margin it needs when prototypes become dependable production systems.